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Speakers
Dan Armbrust
President and Chief Executive OfficerSEMATECH
CV
Title: Exploring New Strategies for Creative Cooperation in Nanoelectronics R&D
Abstract: The dramatic evolution in the semiconductor industry over the last decade, driven by rising costs, constrained resources, and a challenging technology roadmap, has heightened the need for collaboration, as companies facing increasingly difficult technology and investment choices have come together through consortia and alliances to share resources, cost, and risk. Success in new technology introduction over the next ten years will depend on forging even stronger connections between the research, development, and manufacturing communities, and on driving a broader and deeper industrial collaboration that aligns key stakeholders across the entire supply chain.
As an international consortium, SEMATECH's role is to pull innovative research into the industry mainstream, and bring together stakeholders from across the industry ecosystem to solve common infrastructure problems. Based on our experience, this presentation will outline recent examples of successful collaborations in nanoelectronics, and explore new collaborative strategies for the next decade. It will examine the opportunities and challenges such as heterogeneous integration, EUV extendibility, nanodefects, and the post-450mm era that will require new innovations - not only in technology and manufacturing, but also in collaboration. Business models and connections across the nanoelectronics R&D community will continue to evolve as we find new ways to cooperate to accelerate progress and reduce costs.
This can only be achieved by spanning more broadly across regions, extending more deeply into the supply chain, cutting across technology disciplines, and optimizing the use of shared industry R&D centers.
David Arthur
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Gilbert Declerck
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Benjamin J. Eggleton
ARC Centre of Excellence for Ultrahigh-bandwidth Devices for Optical Systems (CUDOS)School of Physics
University of Sydney
CV
Title: Photonic circuits transforming the new information age: Faster, smaller and smarter
Abstract: My talk will review our recent progress in demonstrating nonlinear photonic circuits (photonic chips) for ultrafast all-optical signal processing based on highly nonlinear materials and nanophotonic circuits and structures. I will review the underlying principles of the optical nonlinearity and show how it can be massively enhanced using slow light in photonic crystal circuits. I will also review our recent breakthrough demonstrations of ultrafast all-optical signal processing and waveform analysis and emerging applications of photonic chip based all-optical processing in quantum processing and nonlinear optical phononics (opto-acoustic interactions).
This research was performed as part of the CUDOS Australian Research Council Centre of Excellence program. CUDOS aims to develop the science and engineering to transform photonic integrated circuits into a practical, powerful technology employing optical signal processing to enable critical applications spanning communications, sensing and security. This will enable the Internet to transfer vast amounts of data; it will lead to secure transmission using quantum photonic-based devices, and to the detection of mid-infrared signatures of light from distant stars and complex molecules of environmental or biochemical importance. CUDOS is a collaboration between Australia's leading universities with photonic research programs, The University of Sydney, ANU, Macquarie University, Swinburne University of Technology, RMIT, Monash University and UTS and partner investigators from the world's leaders in photonic research, both globally and locally.
Keywords: photonics, nanophotonics, nonlinear optics, quantum, telecommunications
Anne Emig
CV
Masao Fukuma
Executive Director, Semiconductor Industry Research Institute JapanCV
Title: Nanoelectronics in Smart Society
Abstract: The so called the smart society is expected to need many new applications for electronic devices. Difference compared with the existing ubiquitous society is aiming solutions for the social issues. In this report, important research directions for smart technologies are discussed based on the applications to solve the social issues. They are 'understanding', 'zero-energy', '100-years lasting', 'auto-update` and 'inter-operability/dependability'. Although nanoelectronics have both advantage and disadvantage, this application driven approach can use the only superior characteristics of nanoelectronics than existing electronic devices, then their utilization will be promoted. Many nanoelectronics undertaken in Japan are shown to be potential candidates for smart technologies.
Key words : smart society, understanding, zero-energy, 100-years lasting, auto-update, interoperability, dependability
Kosmas Galatsis
Associate ProfessorMaterial Science and Engineering Department
UCLA
CV
Title: IPWGN Global Update and Report
Abstract: This presentation will update the audience with the International Planning Working Group on Nanoelectronics. The group consists of three regions (USA, Japan and Europe) that aims to stimulate and enhance inter-regional cooperation in nanoelectronics through information organization exchange. The update will highlight research needs of nanoelectronics, will provide a overview of the scope and size of regional nanoelectronics research programs, will discuss potential research gaps and identify areas where collaboration and cooperation between regions will accelerate progress.
Paolo Gargini
Chairman ITRSIEEE Fellow
Intel Fellow
CV
Title: US Industry's Nanoelectronics Initiatives and Results
Abstract: The National Nanotechnology Initiative (NNI) was launched in the year 2000 in the United Sates under Dr. Mike Roco's leadership with the participation of many government organizations. This initiative created a fertile research environment in the United Sates that spread to all universities, leading to a true renaissance in nanotechnology research. Subsequently, the Nanoelectronics Research Initiative (NRI) was launched in 2005 by SIA with the goal of "Demonstrating a novel computing device capable of replacing the CMOS FET as a logic switch by 2020." Four centers of excellence were then sequentially formed: WIN, INDEX, SWAN and MIND. Joint solicitation with NSF has been part of the program from its inception. In addition, in 2008 the National Institute of Standards and Technology (NIST) became a full member of NRI.
Each of the four centers has identified uniquely promising new physical effects that could soon lead to innovative new devices. Exciting and surprising discoveries have already been made by the combined efforts of NRI, NSF, DARPA and NIST, just to mention a few. The highlights of the research will be reviewed, together with future plans, at the INC 8.
Sascha Hermann
Chemnitz University of TechnologyCenter for Microtechnologies
CV
Title: Wafer Level Approaches for Carbon Nanotube Integration beyond CMOS and MEMS/NEMS
Abstract: In this work we give an overview about recent developments in the integration technology of CNTs. We focus on wafer level approaches with the CVD and DEP method for growing as well as depositing CNTs. So that we present methods to manipulate CNT growth structure, growth mode as well as growth inhibition in thermal CVD processes. This is highlighted by a unique growth structure opening new possibilities for CNT integration. Likewise, we show recent developments in scaling up the DEP method on wafer level. We round it up with the fabrication of CNT via interconnects for ULSI circuits and MEMS/NEMS structures containing CNT sensor elements.
Keywords: Carbon Nanotubes, CVD, DEP, wafer level, interconnect, sensor
Marc Heyns
Fellowimec
CV
Title: How to maintain the performance at reduced power in future CMOS
Abstract: Over the last years many new materials have been introduced in advanced CMOS processes in order to continue to progress along the scaling roadmap. Replacing the SiO2/poly-Si stack with deposited high-k gate dielectrics and metal gates was a major challenge in this respect. In the near future even bigger hurdles have to be overcome that will take us beyond the Si roadmap by introducing high mobility channel materials such as Ge and III/V compounds to meet the power and performance specifications of advanced CMOS technologies. This will go together with the introduction of new device concepts such as implant-free quantum well devices or nanowire devices that fully exploit the unique properties of these materials. Ultimately power consumption rather than speed is limiting the scaling roadmap and future technology generations will require a further reduction of the supply voltage.
The use of high-mobility materials with with a smaller bandgap than Si already help in this respect, but the final targets can only be achieved by introducing devices that have a superior subthreshold behaviour. Tunnel-FETs, based on III/V or graphene, can provide superior performance at lower power consumption by virtue of their improved subthreshold behavior. Vertical surround gate devices can be produced from III/V nanowires directly grown on silicon, allowing the introduction of a wide range of III/V materials and functionalities on Si. The combination of new materials and devices will allow to continue the scaling of nanoelectronics beyond the Si roadmap.
Keywords: CMOS, Ge and III/V devices, TunnelFETs, reduced Vdd
Sumio Iijima
Professor (Meijo University)Director (AIST/NTRC)
Senior Research Fellow (NEC Corporation)
Distinguished University Professor (Nagoya University)
CV
Title: Nanocarbon Materials: Their Science and Technology
Abstract: Basic properties of carbon nanotubes as a unique condensed matter have been studied intensively, and now their industrial applications have been searched in various fields of industries where some of killer applications have been looked for. There is some good news of such applications recently. One of important factor for the industrial applications, synthesis of various nano-carbon materials, CNTs and CNHs that we have developed, will be reviewed with the emphasis on the large-scale production [1, 2,3]. Separation of semiconducting single wall carbon nanotubes (SWCNT) and metallic ones from pristine SWCNTs is another important development for the industrialization [4]. A recent challenge in Nano carbon research will be a "low temperature CVD synthesis of flexible graphene sheets substituting ITO films.
Here we shall demonstrate a "roll to roll" growth of an A4-size graphite sheets grown at 300°C using a microwave surface-plasma CVD method [5] and its touch screen application.
I shall introduce structural characterization of nano-carbon materials using atom-resolution electron microscopes. A recent progress in HRTEM technology such as aberration correction and EELS has allowed elemental analysis, distinction of valency and more on individual atom basis measurement [6-8].
1) K. Hata, et al., Science, 306, 1362 (2004).
2) T. Saito, et al., Nanoscience & Nanotechnology, 8, 6153 (2008).
3) S. Iijima, Chem. Phys. Lett., 302, 165 (1999).
4) Huaping Liu, et al., Nat. Commun. 2, 309 (2011).
5) J. Kim, et al., APL, 198, 91502(2011).
6) K. Suenaga, et al., Nature Nanotech. 2, 358 (2007).
7) C. H. Jin, et al., PRL, 102, 195505 (1)-(4) (2009).
8) K. Suenaga et al., Nature, 468, 1088 (2010).
Keywords: nanocarbon, carbon nanotubes, carbon nanohorn, graphene, TEM
Toshihiko Kanayama
Vice-President,Director General for Information Technology and Electronics, Nanotechnology, Materials and Manufacturing
National Institute of Advanced Industrial Science and Technology (AIST)
CV
Title: Nanoelectronics research activities in TIA-nano
Abstract: The nanoelectronics is one of the six major research domains of TIA-nano. Its main mission is to create new functionalities and applications in electronics by applying nanotechnology to the Si CMOS platform, i.e., fully utilizing new functions arising from well-controlled nanoscale materials and structures. This is inherently a cross-disciplinary field requiring integration of various technologies, and thus requires state-of-the-art CMOS R&D facilities which accept exotic materials and processes. To meet this requirement, several facilities are provided in TIA, where intense collaborations are conducted between various sectors of industries and academia. The largest one is the AIST Super Clean Room, in which a 300-mm wafer fabrication line is applied to various researches from exploratory research, through demonstration and evaluation of integration, to pilot production of innovative prototype devices.
Actually, six major R&D projects are being conducted in TIA nanoelectronics. In particular, aiming at extremely low power operations, many fruitful results have been obtained; e.g., high-mobility channel transistors and steep-slope transistors for low-voltage logic, BEOL non-volatile memories, and Si-photonics devices for low-power optical interconnect and network.
Key words: CMOS platform, high-mobility channel, steep-slope transistors, non-volatile memories, Si photonics
Shinichirou Kimura
Vice project leaderLow-power Electronics Association & Project (LEAP)
CV
Title: Recent Progress in Low-power Electronics Association & Project (LEAP) Aiming for Low Power Electronics
Abstract: Reduction of power dissipation of ICT and electronics equipment is a key issue to achieve a low-carbon society. For this purpose, The Low-power Electronics Association & Project (LEAP) was inaugurated on May 21, 2010, and the "Ultra low voltage device project for low-carbon society" was started on Aug. 6, 2010. The project aims to develop new non-volatile backend memories and switching device having new functions, taking advantage of 300-mm Si facilities in AIST in Tsukuba. In addition, it aims to develop new basic technologies such as carbon interconnects with low resistivity and SOI transistors characterized by small variability and back bias scheme.
Although heavy damages by the Great East Japan Earthquake caused delay in the device fabrication, we were able to show a steady progress in terms of the selection of materials, determination of the device structures and its manufacturing processes. BEOL (Back-end of Line) platform, in particular, by which the new devices are embedded in CMOS, was successfully established. Some devices had already been integrated on 300-mm wafers supplied from a product manufacturing line, owing to unprecedented efforts of those concerned. In this presentation, we would like to talk about recent progresses of five themes paying attention to their core technologies we think them inevitable for enhancing power reduction.
The project is one of the nano-electronics R&D projects in Tsukuba Innovation Arena (TIA) and is supported by the Ministry of Economy, Trade and Industry (METI) and New
Teruo Kishi
ChairmanThe Executive Board
Tsukuba Innovation Arena for Nanotechnology
CV
Title: Tsukuba Innovation Arena for Nanotechnology (TIA-nano) --Participation of new leading member and recent progress of TIA-nano--
Abstract: 4 years have passed since the global nanotechnology research and education complex (Tsukuba Innovation Arena for nanotechnology :TIA-nano) was established in Tsukuba City, and more than 60% of planned budgets have been spent for the investment. We realized that now is the right time, when we must create a common value toward global business. At this precious moment, from this April, the new member "High Energy Accelerator Research Organization" participated TIA-nano as the leading organization, and it is known as one of the world's leading accelerator science research laboratories, using high-energy particle beams and synchrotron light sources to probe the fundamental properties of matter.
As the progress, TIA-nano started many new research projects including EUV lithography research by EIDEC (EUVL Infrastructure Development Center) and Green sensor-net research by the development partnership of NMEMS and new partnership programs including MEMS foundry for small volume (MNOIC) and sample supply of Carbon Nanotube to explore novel applications. In the nano-electronics field, the non-volatile device of the resistance change model that can be applied on the wiring layer of the LSI (Back-End Of Line :BEOL) has been developed. Moreover, BEOL (Back-End Of Line) non-volatile, resistivity-change device and the basic integration technologies were developed including nano-carbon interconnects and variation-free MOS transistor/ platform enabling operation at 0.4V or below with reduced power dissipation for IT equipments.
TIA-nano, as the "global" nanotechnology complex, is implementing the activities to function as an innovation engine of the World.
Weon-Bae Ko
ProfessorDepartment of Chemistry
Sahmyook University
CV
Title: Status on the Nano Education and Asia Nanotech Camp 2011 in Korea
Abstract: I will have a lecture on introduction of the nanotechnology education and Asia Nanotech Camp 2011 in Korea according to the following contents;
1. Status of nanotechnology researcher.
2. Number of nanotechnology publication paper by country (SCI).
3. Number of registered patents for each country.
4. Nanotechnology curriculum and text book development.
5. Lecture series focused on nanotechnology.
6. E-nano school system construction and on line lecture service.
7. Nano measurement and analysis professional training for beginner.
8. Nano education program for the public and students.
9. Perform nano education program as a co-session in international symposium of Nano Korea 2010.
10. Asia Nano Forum - Education program.
11. Report of Asia Nanotech Camp 2011 in Korea.
Keywords: Nano Education, Nanotech. Textbook, e-Nano School, Nano Korea 2010, Asia Nano Forum, Asia Nanotech Camp 2011, Korea
*E-mail: kowb@syu.ac.kr, tel: +82-2-3399-1700, fax: +82-2-979-5318
Tadahiro Kuroda
ProfessorElectrical Engineering
Keio University
CV
Title: ThruChip Interface for Energy Efficient Electronics
Abstract: Performance bottleneck is often seen at chip bandwidth because device scaling improves chip performance in proportion to area but pin bandwidth to periphery. The shortage of the bandwidth has been made up by high-speed circuits in I/O, which is reaching the end of limit and causing rapid increase in I/O power dissipation. The deceleration of Moore's law, on the other hand, brings an opportunity of opening a new era of 3D system integration. Chip area rather than periphery should be used for I/O. TSV using chip area has advantages over wire-bonding but it is not available yet for commercial use. This paper describes a wireless inter-chip link using inductive coupling in the near field, namely ThruChip Interface (TCI). TCI is a digital CMOS circuit solution in a standard CMOS technology. It is much cheaper than TSV but bears comparison in performance. Energy consumption is 0.01pJ/b, two orders of magnitude lower than that of the conventional high-speed links such as DDR. TCI reduces power dissipation of Solid-State Drive (SSD) to 1/3. The power reduction is mainly attributed to multi-drop bus by through-chip inductive coupling. A constant magnetic-field scaling will further improve cost/performance by exponential rate.
Key words: inductive coupling, ThruChip Interface, near field, chip stacking, TSV
Hubert Lakner
Fraunhofer Institute for Photonic MicrosystemsCV
Ryutaro Maeda
Director of UMEMSME (Research Centre of Ubiquitous MEMS and Micro Engineering)National Institute of Advanced Industrial Science and Technology
CV
Title: Paper title: TIA (Tsukuba Innovation Arena)-NMEMS -Open Innovation platform for low carbon and safe society-
Abstract: MEMS (Micro electromechanical systems) or Nano technology is expected as one of the most promising R&D fields for the future business success. However R&D investment to MEMS facility is too heavy even for the large scale companies. Although MEMS foundry services by private companies have been introduced in these ten years in Japan, most of their facilities are still in the size of 6 inches, and the Japanese capability of mass production of MEMS devices are rather behind compared by other advanced countries.
This is the reason why AIST has just introduced the new large wafer scale facilities including 8 inches MEMS line and 12 inches TSV line. The facilities are called as TKB812 and started the operation from the end of 2010, where all the energy and materials consumptions are monitored by networked sensing for low power and minimal materials consumption management.
With the use of networked sensing and real time monitoring of electricity power, we had succeeded in the reduction of more than 30 % peak value of electricity energy consumption. We hope this system will help us to overcome our difficulty of electricity power loss induced by the Earthquake and the consequent stops of nuclear power plant stop in Japan.
Key word: MEMS, Commercialization, Large wafer, Green Sensor Network, Energy Management, Low Carbon Society
George Maracas
Program Director, Energy, Power, and Adaptive Systems (EPAS) ,Division of Electrical, Communications, and Cyber Systems (ECCS)
Cyber Systems (ECCS)
National Science Foundation (NSF)
CV
Title: Nanotechnology for Clean Sustainable Energy
Abstract: Global energy use is predicted to double by the year 2050 because of population growth and an increasing percentage of citizens adopting high technology and electric power-intensive lifestyles. Commensurate with this growth in demand is an increase in CO2 emissions that the additional energy will produce. Technologies are needed that will increase efficiency of alternate energy collection and conversion and also provide innovative ways to store and interface it to the electric grid. This talk will discuss developments in nanotechnology science and engineering that are contributing to the fields of clean sustainable energy. Developing sustainable solutions to energy challenges requires adopting a life cycle approach to science which considers availability and use of raw materials through innovation and scale-up while understanding the environmental and societal factors that will be impacted by its widespread adoption.
Kunichi Miyazawa
Fullerene Engineering Group,Advanced Materials Processing Unit,
National Institute for Materials Science
CV
Title: Synthesis of fullerene nanomaterials by liquid-liquid interfacial precipitation method and their properties and applications including superconductors
Abstract: A variety of low-dimensional nanomaterials composed of fullerene molecules and fullerene derivatives have been synthesized since the formation of C60 nanowhiskers in a lead zirconate titanate (PZT) solution added with C60 in 2001. Those fullerene nanomaterials can be synthesized by using a simple method called "liquid-liquid interfacial precipitation method (LLIP method)". In the LLIP method, a poor solvent of fullerene is placed on a good solvent solution of fullerene. The nucleation of fullerene crystals initially occurs at the liquid-liquid interface through the interdiffusion of solvents that causes the increase in supersaturation of fullerene, and low-dimensional fullerene crystals such as nanowhiskers, nanotubes and nanosheets are formed by self-assembling during the homogenization process of solution.
On the other hand, the diaphragm LLIP method has been developed by using a porous alumina membrane that separates the two solutions and enables the growth of vertically aligned fullerene microtubes and whiskers. A variety of application studies for field-effect transistors, solar cells, chemical sensors, photoluminescence devices and so forth have been performed using the fullerene nanowhiskers, nanotubes and nanosheets. Last year, the C60 nanowhiskers doped with potassium were discovered to become superconductive with a Tc of 17 K and exhibited a very high critical current density greater than 105 A/cm2. As shown above, the LLIP method is a powerful technique to produce various fullerene nanomaterials that will be useful in electronics, optics and energy applications, including superconductors.
Key words : fullerene nanowhisker, fullerene nanotube, fullerene nanosheet, LLIP method, superconductor
Masaaki Niwa
Professor, Graduate School of Pure and Applied SciencesUniversity of Tsukuba
CV
Title: Cultivation of Human Resource in Nano-technology and Worldwide collaboration
Abstract: Cultivation of human resource is a key issue for Nanotechnology. This is because interdisciplinary or integrated research is absolutely imperative for "Nano-technology". There are opportunities that open up the impasse of current technology by a fusion of different area, i.e., industry, academia and government, and lowering the disciplinary boundaries such as electronics and biology. In order to achieve this breakthrough, it is necessary to adjust the social system including new education system at university, creation of a resonance field among private-sector companies, national institutes and universities as well as new recruiting system at industry.
Main purpose of this activity at university is to cultivate world-class human resource who can take part in a global community.
In the presentation, importance of "Worldwide Collaboration" followed by recent matter of concern in Japan, and attempts at University of Tsukuba, i.e., "Honors Graduate Program" and "International Student Exchange Program" are introduced. The Honors Graduate Program is operated under University/Industry/National Research Institute collaborative research program in Tsukuba, cooperating with TIA (Tsukuba Innovation Arena). The collaborative partners are National Institute of Advanced Industrial Science and Technology(AIST), National Institute for Materials Science(NIMS), High Energy Accelerator Research Org.(KEK) and Private-sector companies.
Key words: Human resource, worldwide collaboration, Honors Graduate Program, International Student Exchange Program, Resonance Field, Collaboration Coordinator
Tetsuji Noda
Director, NIMS Nanotechnology Support NetworkNational Institute for Materials Science (NIMS)
CV
Title: Activities of Nanotechnology Network Japan and Programs fostering Young Researchers and Technical staffs
Abstract: "Nanotechnology Network Japan" sponsored by MEXT started in 2007 for five years following "Nanotechnology Support Project of 2002 -2006. The project offers academic, business, and governmental nanotechnology researchers the opportunities to use facilities and equipments of 13 sites with high-level technical supports covering four areas of nano-fabrication, nano-characterization, molecular synthesis, and analysis under extreme conditions. The project aimed at generating high quality research results as well as leading to create innovations. NIMS nanotechnology Network center operating as a coordinator of the program, has missions of providing informations on user facilities and research topics to all researchers through portal website and web magazine, and promoting to foster young researchers and technical staffs.
The activities cover domestic and international schools including iREU and iREG programs with NNIN, young researchers exchange program with NSF, practical experience program for technical staffs between 13 sites. International programs with EU and Asian countries will be also planned in a next new project.
Keywords: Nanotechnology, Facility network, Nano-Fabrication, Nano-Characterization, Molecular Synthesis, Educational Program
Hajime Okumura
Director,Advanced Power Electronics Research Center
National Institute of Advanced Industrial Science and Technology
CV
Title: Recent Progress of Novel Semiconductor Power Electronics and Related National Projects in Japan
Abstract: Nowadays, energy saving in electric power is one of the most urgent issues for sustainable development of the human society. Power electronics is a technology for conversion and control of electric power, and believed to be quite promising for electric energy saving. From the viewpoint of power electronics innovation, widegap semiconductors such as SiC and GaN have been recently attracted much attention, because these materials exhibit superior material properties most suitable for high-power switching devices, which are key components of power electronics equipment. For a long time, technological levels of widegap semiconductors has been behind those of conventional semiconductors such as Si and GaAs, due to the difficulty in crustal growth and device fabrication etc. However, remarkable progresses have been achieved in these several years.
In this talk, I will briefly introduce the importance of power electronics and related widegap semiconductor technology, including several national projects presently conducted in Japan.
Key word : power electronics, widegap semiconductor, SiC, GaN, electric power conversion, power semiconductor device
Mike Roco
Senior Advisor for NanotechnologyNational Science Foundation (NSF)
National Nanotechnology Initiative (NNI)
CV
Title: SCOPE OF INC8
Abstract: The International Nanotechnology Conference on Communication and Cooperation was initiated in 2005 (1) to present overviews on major national and industry R&D programs in Europe, Japan and United States; (2) exchange of ideas between leaders of R&D programs and organizations; (3) address long term and global research and societal needs; (4) promote partnerships between industry, academe and government in the three regions; and (5) international collaborations between the annual events. The 8th annual conference in Tsukuba maintains a focus on nanoelectronics and cross-disciplinary research in nanotechnology and addresses societal needs in regional, topical and poster sessions. Several statistics since 2005 and suggestions for the future are presented. The conference series has to respond to the accelerated changes in the development of nanotechnology and converging technologies, encouraging new models for education and innovation, and bringing new partners and younger contributors in the activity. This conference is a part of the global governance of nanotechnology where supporting transforming tools, inclusion, partnerships, responsible development and foresight are essential.
Mike Roco (We-1)
CVTitle: NANOTECHNOLOGY SIGNATURE INITIATIVES IN THE UNITED STATES (2011-2015)
Abstract: Twenty years is the estimated time scale to develop nanotechnology from basic interdisciplinary concepts in 2000 to create a general purpose technology with mass and sustainable use by 2020 ("Nanotechnology Research Direction" NSTC 1999). The outcomes at ten years generally are on target, and an updated vision for development of field by 2020 has been prepared ("Nanotechnology Research Directions for Societal Needs in 2020" Springer 2011, available on www.wtec.org/nano2/). Priorities of the U.S. National Nanotechnology Initiative have been grouped and are funded under several "Signature initiatives" since 2011. Three such initiatives currently are funded (Nanoelectronics for 2020 and Beyond; Sustainable Nanomanufacturing; Nanotechnology for Solar Energy), two are in development in 2012 (Nanoinformatics; Nanosensors), and others are under consideration. There is an increased focus on nanoscale science and engineering integration, convergence with biology and other scientific domains, and establishing a general-purpose technology. The labor and markets are estimated to double each three years, reaching a $3 trillion market encompassing 6 million jobs by 2020. It will be imperative over the next decade to focus on knowledge, material, global, and moral progress of nanotechnology development.
Barbara Rhode
CV
Marcin Sadowski
European Commission,DG for Research and Innovation, Unit G3 "Materials", Brussels, Belgium
CV
Title: A European approach to Research and Innovation on Key Enabling Technologies
Abstract: In 2010, the European Commission defined a clear vision, objectives and targets, covering the coming 10 years, for Europe to become more globally competitive and more sustainable to the benefit and well-being of all its citizens. To realise this vision, the European Commission has set up a strategy, EU2020, for "smart, sustainable and inclusive growth". Research and Innovation is considered a key element in this strategy.
The newly established proposal for the future European Framework Programme for Research, Development and Innovation, HORIZON 2020, has as a main target to elaborate world-class advanced research and innovation results, including infrastructures. HORIZON 2020 aims to establish and increase European scientific leadership in many fields, to contribute to the global competiveness of the European industry and to the larger socio-economic policy objectives of the Union. Importantly, Europe has a deficit in transferring research into market advantages.
National Governments and the Commission have acted on this situation and declared five technologies as Key Enabling Technologies (advanced materials, nanotechnology, micro-nanoelectronics and semiconductors, photonics, biotechnology, and advanced manufacturing as a cross cutting technology). These technologies are considered strategic for the competitiveness of Europe and to implement several of the large political and social European objectives.
Patrice Simon
ProfessorUniversité Paul Sabatier
CV
Title: Carbon-based micro-supercapacitors
Abstract: Electrical Double Layer Capacitors (EDLCs), also known as supercapacitors, are one of the most promising electrochemical energy storage devices for high power delivery or energy harvesting applications [1]. EDLCs store charge through the reversible adsorption of ions from an electrolyte onto high surface area carbons, thus charging the double layer capacitance. Large-size ECs are already used today for power supply and energy harvesting in various applications such as aeronautics, tramways, HEVs (c) [1]. However, the recent boom in multifunction portable electronic equipment and the increasing need for wireless sensor networks for the development of smart environments has raised the problem of developing sufficiently compact and/or flexible energy storage.
Designing efficient, miniaturized energy-storage devices that can achieve high energy delivery or harvesting at high discharge rates with a lifetime that matches or exceeds that of the machine being powered remains a challenge. Integrating the storage element as close as possible to the electronic circuit (directly on a chip) is another challenge.
This talk will present an overview of the results obtained using carbons in micro-supercapacitors. We will show results obtained using exohedral and microporous carbons, as well as bulk carbon films in micro-devices prepared from different methods. The performance achieved to date addresses the need for microscale energy storage in numerous areas where electrolytic capacitors cannot provide sufficient volumetric energy density, such as nomad electronics, wireless sensor networks, biomedical implants, active radiofrequency identification (RFID) tags and embedded microsensors.
References[1] P. Simon and Y. Gogotsi, Nature Materials, 7 (2008) 845-854.
Junichi Sone
Executive Vice PresidentNational Institute for Materials Science
CV
Title: Tsukuba Innovation Arena Nano-Green "Open innovation platform for environment and energy technologies"
Abstract: We are facing serious energy and environment issues such as a global warming, exhausting available fossil fuels, and consuming precious natural resources. It is hard for a single corporation or a single research institution to create technological innovations to solve those issues, and thus a global open innovation where wisdom is summoned from all over the globe is highly required. Tsukuba Innovation Arena (TIA) Nano-Green has been established to create innovative technologies for environment and energy based on material technologies accumulated up to the present as a core technology in NIMS. It is organized as an open innovation platform where collaborations among industries, AIST, and the University of Tsukuba, centering on NIMS are conducted. In the TIA Nano-Green, research and development on the technologies to control the electric and thermal energy flows is carried out by using innovative energy conversion and storage materials for secondary battery cells, fuel cells, solar cells, thermoelectric conversion devices, and so on. New magnetic materials are also pursued as a key material to realize a dramatic reduction of the consumption energies in the storage or memory devices. These research activities are conducted in the new environmental research building just completed at the Namiki-Site of NIMS at the end of March this year.
Clivia M. Sotomayor Torres
ICREA Research ProfessorPhononic and Photonic Nanostructures Group
Catalan Institute of Nanotechnology (CIN2-CSIC)
CV
Title: ECOSYSTEMS TECHNOLOGY & DESIGN for NANOELECTRONICS: an experience in Europe
Abstract: We present the project NANO-TEC (Ecosystems Technology and Design for Nanoelectronics). The aim of NANO-TEC is to address the gap between technology and design in Nanoelectronics in the area of Beyond CMOS. While a recognised European strength is in heterogeneous integration, the academic community is also very strong in research addressing ways to carry out information processing operations using different concepts, state variables and associated technologies. A second aim of NANO-TEC is to consolidate and strengthen the academic community in Europe in the area of Beyond CMOS.
This trend is presently decoupled from the research in design and it is this gap which weakens the impact of the progress being made in Beyond CMOS, since ways to realise devices operating under real conditions in a competitive manner to existing technologies are simply not viable without a design counterpart.
To this end NANO-TEC carries out a continued consultation and analysis of research needs and trends based on a workshop series with invited experts from the Americas, Asia and Europe covering topics such as Beyond CMOS device concepts and design, benchmarking and a SWOT analysis of new devices. We will report on progress made so far towards our stated aims.
NANO-TEC is a project funded by the European Commission under number 257964.
For more information: www.fp7-nanotec.eu
Kazunobu Tanaka
Principal Fellow,Center for Research & Development Strategy(CRDS),
Japan Science & Technology Agency (JST)
CV
Title: Japan's R&D Strategy of Nanotechnology
Abstract: The promotion system of science and technology (S&T) policy in Japan and strategy for nanotechnology/materials are addressed at the beginning of the presentation. In this category, the main issues of the 4th S&T Basic Plan of Japan are introduced, which were determined by the Japanese Cabinet in August 2011. Moreover, the trends of budget related with S&T as well as nanotechnology/materials are denoted. Platforms on nanotechnology/materials in Japan are subsequently shown including Tsukuba Innovation Arena (TIA), Nano Network, and inter-ministerial coordination between MEXT and METI. The 4th S&T Basic Plan positions "Green Innovation" for environment and energy and "Life Innovation" for medical care/nursing care/health as two major pillars of growth, in addition to the Recovery Initiative from the Great East Japan Disaster and the Fukushima nuclear power plants accident. The "Green Innovation" as well as "Life Innovation" includes the research field of nanotechnology/materials as a powerful tool to realize the innovations. As a technology related with the nanotechnology/materials to contribute energy revolution in Japan, new magnetic devices and the other technologies are described. Nanotechnology/materials to contribute the reduction of rare earth consumption are also explained. In addition, trilateral cooperation on rare earths is addressed. Finally, the status of nanotechnology/materials in the structure for the promotion of 4th S&T Basic Plan is mentioned briefly.
Key-words: 4th Science and Technology Basic Plan, Platforms on nanotechnology/materials, Promotion of green innovation
Olivier Thomas
Senior Research EngineerCEA-LETI Laboratory
CV
Title: FDSOI technology on Ultra thin BOX, a compelling solution for sub-28nm mobile SoC generations
Abstract: The strong growth of new mobile multimedia devices (smartphone, tablet, notebook, etc.) requires high-performance, low-power system-on-chips (SoC). These SoCs will have very different needs than past mobile processors. High-clock frequency (HS) has to be achieved simultaneously with low-operation supply voltage (VDD) and low stand-by leakage (LSTP). However, when approaching sub-28nm technology nodes, traditional planar-bulk technologies cannot meet these requirements due to physical limits degrading the electrostatic gate to channel control (ION, IOFF) and increasing the transistor VT variations (random dopant fluctuations, lithography limitations, etc.). To overcome these issues, new device architectures, new materials and advanced low operating design solutions are being investigated extensively.
Among these solutions, Ultra-Thin Body and Buried oxide (UTBB) Fully-Depleted (FD) silicon-on-insulator (SOI) transistor with a high-k metal-gate stack appears as an excellent response to the needs of the next sub-28nm HS/LSTP SoC generations. This is due to the excellent short-channel electrostatic control (ION/IOFF ratio), low leakage current (IOFF), immunity to random dopant fluctuation (VT variability) and compatibility with bulk design platform (planar technology) of UTBB-FDSOI. This presentation aims to give an overview of UTBB-FDSOI technology from transistor to design level. After a brief recap of the Bulk scaling issues, the FDSOI digital transistor performance will be shown and promising specific design solutions taking maximum advantage of the potentialities of FDSOI will be discussed.
Key words: FDSOI, Low power, High performance, Digital, SRAM
Hisatsune Watanabe
PresidentEUVL Infrastructure Development Center, Inc. (EIDEC)
CV
Title: Evolution of Nanoelectronics for Human Life Convenience
Abstract: Nanoelectronics evolved by Nanoscience and Nanotechnology will be classified into three categories in future. One is the evolution of the performance by more miniaturized device integration, the second is the multi-functionalization by novel-device fusion, and the third is the energy management devices by drastic energy efficiency improvement. In each category, it has a kind of evolution by driving-technology or driving-science. The first one (More integration) needs the lithography evolution. The second one (Multi-functionalization) needs the low-cost fabrication evolution, the third (Energy management) needs the conversion efficiency evolution. Global collaboration is inevitable for the creation and spread of the nanoelectronics markets to advanced and emerging countries, because the priority of the necessity of three evolutions will be strongly dependent on each country's national condition.
Energy efficiency issue will be the first priority for rapid population-increasing countries, while the population-decreasing country like Japan needs the multi-functionalized system for safe and healthy life of aged persons. Big ICT-power consuming countries have obligation to strongly save and reduce the ICT infrastructure electric power consumption for not only self-purpose but also for large-population emerging countries. We will need a strategic global discussion for the healthy development toward Nanoelectronics-based life on the earth.
Key words: Nanoelectronics, three categories of the evolution, more integration, multi-function, energy efficient improvement, market development by global collaboration
Jeff Welser
Director,SRC Nanoelectronics Research Initiative
CV
Title: Update on the U.S. Semiconductor Industry's Nanoelectronics Research Initiative
Abstract: Since 2006, the Nanoelectronics Research Initiative (NRI) has been actively funding work at universities across the U.S. with one specific mission: Demonstrate novel computing devices capable of replacing the CMOS FET as a logic switch in the 2020 timeframe. These devices must show significant advantage over FETs in power, performance, density, and/or cost to enable the semiconductor industry to extend the historical cost and performance trends for information technology. In the current phase of the work, each of the NRI centers has been focusing on just 2-3 device options, with teams looking at everything from the basic materials and physics, to device and circuit design. The primary goal is to collect sufficient data on each device to see if it could pose a viable option for extending scaling beyond CMOS, with an emphasis on gathering experimental results to verify the theoretical models. Using these results to refine the on-going benchmarking efforts guides the work by showing where the devices offer the most potential advantage (power) and where they have the greatest challenges (speed). This talk will give an overview of the latest status of this work, and an outlook of what we foresee for the next phase.
Andreas Wild
CVTitle:
Abstract:
Eli Yablonovitch
Professor of Electrical Engineering & Computer Sciences,The James & Katherine Lau Chair in Engineering, University of California, Berkeley
CV
Title: Energy Efficient Electronics Science; Searching for the Milli-Volt Switch
Abstract: Tunneling FETs, a key approach for reducing the energy consumption in electronic circuits, have been in research for many years, but the results have been disappointing. Simulation predicts phenomenal results but experimental results are far worse. A large record of device results came from a keen focus on technology development and device optimization, without an adequate attention to fundamentals. Moreover, the concept of the TFET itself is still in flux, with various mechanisms proposed. The lack of a sound scientific foundation has impeded the achievement of promising results.
One of the requirements for TFET progress will be played by the dimensionality of the tunneling structure. This must incorporate a 2d 2d pn junction to enjoy a favorable step-function like switching characteristic. Moreover, the quantum confinement in the 3rd dimension promotes high tunneling probability. Even with the 2d 2d geometry, a new concerted effort will be needed to elucidate the physics of energy bandgap sharpness both theoretically and experimentally.
In this talk I will address all the new physics that will be needed for fulfilling the promise of the TFET.
Reference: http://arxiv.org/abs/1109.0096
Keywords: energy, efficiency, tunnel, FET, junction, dimensionality
Akira Yoshino
Fellow, Asahi Kasei Corp.CV
Title: "Lithium ion battery and nanotechnology"
Abstract: The lithium-ion battery (LIB) is a secondary battery that uses a non aqueous electrolyte with carbon as the negative electrode and a transition metal oxide containing lithium ion as the positive electrode. This new battery system was invented in 1985. The use of a nonaqueous electrolyte allowed the cell voltage of the LIB to be raised to 4.2 V. This major leap in cell voltage enabled smaller size and lighter weight.
The conventional positive materials are LiCoO2 and LiMn2O4, and new positive materials such as LiFePO4 and Li (Ni1/3Mn1/3Co1/3)O2 have been developed and begun to be used recently. The negative materials are carbonaceous materials such as graphite and hard carbon.
The positive material is coated on Al foil current collector and negative material is coated on Cu foil. These electrodes are fabricated by mixing active materials (positive or negative material) with binder resin solution and coated on current collector foil and dried.
It is the most important point in LIB technology that all particles in electrodes must be connected electronically. Small amount of electronic conductive additive is added to improve electronic connection of active material particles. The most effective electronic conductive additive is VGCF (Vapor-phase Grown Carbon Fiber) which is typical example of electronic conductive nanofiber.
Key words: Lithium ion battery, Anode materials, Cathode materials, VGCF,